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Design techniques for ultra low voltage CMOS continuous-time filters and continuous-time sigma-delta modulators

机译:超低压CMOS连续时间滤波器和连续时间sigma-delta调制器的设计技术

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摘要

In recent years, the increasing market and the increasing need of battery-operated portable equipment have pushed the industry to put much more efforts on developing new circuit techniques and new circuit structures to design circuit that can operate at very low supply voltages and with reduced power dissipation. Reducing power supply is a natural solution to reduce power consumption. However, reducing power supply does not always mean almost the same performance and low power consumption. All of the above facts have produced the urgent necessity to find new circuit design techniques that can produce circuits operating at power supply voltage in the range of 1V to 2V.;In this dissertation, a technique that can be used to design low voltage CMOS continuous-time analog circuits is proposed. Some biasing current sources are added to the inverting or non-inverting opamp terminals such that the opamp input common-mode voltages could be shifted close to one of the supply rails for allowing low voltage operations.;A digital frequency and Q tuning technique is proposed for low-voltage active RC filters that uses programmable capacitor arrays (PCAs). The proposed technique does not require any peak detectors, which are difficult to implement at low-voltage.;A direct digital background tuning technique for the notch frequency of continuous-time sigma-delta modulator is proposed to solve the large SNR loss problem caused by the deviation of the actual notch frequency from the desired value due to process and temperature changes.;To demonstrate the proposed low voltage design technique, the frequency and Q tuning technique, and the notch frequency tuning technique, a 1V continuous-time filter and a 1.2V continuous-time band pass sigma-delta modulator prototypes are designed, fabricated and tested. For a 5 kHz sine wave input signal, the filter achieves a THD of -60.2 dB for a peak-to-peak output voltage of 600 mV. The measured power consumption for the filter alone consumes about 0.52mW for a supply voltage of +/-0.5V. The measured DR for the 1.2V modulator is about 40dB(6.5bit) and the peak SNR is 44dB(7bit). The power consumption is 2.1mW.
机译:近年来,不断增长的市场和对电池供电的便携式设备的需求不断增长,促使业界投入更多的精力来开发新的电路技术和新的电路结构,以设计可在非常低的电源电压和降低的功率下工作的电路耗散。减少电源供应是降低功耗的自然解决方案。但是,减少电源并不总是意味着几乎相同的性能和低功耗。以上所有事实都迫切需要找到新的电路设计技术,以产生可在1V至2V的电源电压下工作的电路;本文研究了一种可用于设计低压CMOS连续电路的技术。提出了实时模拟电路。在偏置或同相运算放大器端子上增加了一些偏置电流源,以便可以将运算放大器输入共模电压移至靠近电源轨之一以允许低电压工作。提出了一种数字频率和Q调谐技术适用于使用可编程电容器阵列(PCA)的低压有源RC滤波器。所提出的技术不需要任何峰值检测器,这些峰值检测器很难在低压下实现。;针对连续时间∑-Δ调制器的陷波频率,提出了一种直接数字背景调谐技术,以解决由噪声引起的大SNR损耗问题。由于工艺和温度的变化,实际陷波频率与期望值的偏差。;为了演示所提出的低压设计技术,频率和Q调谐技术以及陷波频率调谐技术,一个1V连续时间滤波器和一个设计,制造和测试了1.2V连续时间带通sigma-delta调制器原型。对于5 kHz正弦波输入信号,对于600 mV的峰峰值输出电压,滤波器可实现-60.2 dB的THD。对于+/- 0.5V的电源电压,仅滤波器测得的功耗就消耗约0.52mW。针对1.2V调制器测得的DR约为40dB(6.5bit),峰值SNR为44dB(7bit)。功耗为2.1mW。

著录项

  • 作者

    Huang, Huanzhang;

  • 作者单位
  • 年度 2001
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  • 原文格式 PDF
  • 正文语种 en
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